The invention relates generally to semiconductor lithography, and particularly to controlling overlay offset errors.
A semiconductor device is typically built up of a number of levels which overlie each other. In the usual case, the registration of one layer with the next is not perfect, i.e., there is some overlay offset between successive layers. For any given semiconductor device, there is a parameter corresponding to the total amount of offset which can be tolerated for the device as a whole, known as an overlay budget.
In the prior art, it is known to provide offset error control which compensates for those factors which are involved in the lithography operation itself. However, effects which are external to the lithography operation can also affect offset, and the prior art has not addressed such problem. In particular, effects which occur in the processing of the wafer which takes place after the lithography operation is completed can affect overlay offsets. By way of a specific illustrative example, a chemical-mechanical polishing (CMP) tool having a rotating pad may be used to flatten and polish a level before the next level is built. It has been observed that such tool may add a rotational offset to the level polished, which if not compensated for will adversely affect the placement of each successive layer. There are actually many processing factors which can affect overlay offset, and by way of non-limitative examples these include non-uniform etching, the specific type of film being processed, and the state of a sputtering tool which is used to accomplish metal deposition.